DocumentCode :
3413105
Title :
Minimization of the accumulated phase change at the input of SDH/SONET desynchronizers
Author :
Antry, C.B. ; Owen, Henry L.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
1996
fDate :
27-29 Mar 1996
Firstpage :
315
Lastpage :
320
Abstract :
The minimization of jitter and wander in transmission systems such as SDH/SONET networks has received a great deal of attention. Minimization techniques which may be employed in the synchronizer, pointer processor, and desynchronizer have been proposed. At the input to a desynchronizer in a classical SDH/SONET network, a large peak-to-peak value of the accumulated phase change exists. This is primarily caused by gapped effects such as the 32/35 effect when the network is transporting a VC-12. After reviewing the jitter and wander causing components in an SDH/SONET network, this paper proposes and evaluates a method that compensates for the 32/35 effect. This new method reduces the peak-to-peak accumulated phase change by more than 50% in the VC-12 case. This same technique may be applied to SDH/SONET networks transporting other VCs
Keywords :
SONET; jitter; minimisation; synchronisation; synchronous digital hierarchy; 32/35 effect; SDH/SONET desynchronizers; VC-12; gapped effects; input; jitter; minimization; peak-to-peak accumulated phase change; pointer processor; synchronizer; transmission systems; wander; Circuits; Clocks; Detectors; Jitter; Minimization; Phase detection; SONET; Synchronization; Synchronous digital hierarchy; Virtual colonoscopy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computers and Communications, 1996., Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-3255-5
Type :
conf
DOI :
10.1109/PCCC.1996.493651
Filename :
493651
Link To Document :
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