Test floor verification of multiprocessor hardware

Verification of multiprocessor (MP) system hardware on the test floor for coherence violations is a challenging problem because internal signals are not as readily available as they are in simulation models. Furthermore, in high performance MP systems which employ weak ordering, races between accesses to the same coherence granule can result in non-deterministic results, thereby adding to the difficulty. Therefore, a common verification practice has been to either allow false sharing only or restrict multiple processors from accessing the exact same location without using some form of a “barrier” around the shared location. This allows the execution results to be deterministic so that they can be predicted for static checking at the end of the test program. The paper presents a methodology for detecting coherency violations in weakly ordered multiprocessor systems with arbitrary streams of instructions and without restricting the level of sharing by the processors. This verification is performed under the native operating system of the system under test. In our methodology, only a weak relative ordering of instruction issuance and completion times of loads are sufficient. The method ensures that data returned for each different load from the same processor is stored in a different register each time until no more new registers are available, at which point a program interrupt is generated and the results at that time verified across the system. The test vectors are designed to make full use of the different registers in the system. This technique defines a maximal window during which exact ordering violations are checked. The methodology described here also establishes a process that applies equally well to simulation models as well as floor testing and is 100% portable across the two environments