Title :
Maximal multiple fault coverage using single fault test sets
Author :
Yousif, Abdel-Fattah ; Gu, Jun
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Abstract :
In this paper, an analysis based on the sensitization structure behavior in the existance of multiple faults for the general class of combinational circuits is presented. The analysis is based on partitioning the set of primary inputs into three subsets Se (excitation set), Sp (persistency set), and Sc (control set). The problem of augmenting a single fault test set to obtain a maximal multiple fault coverage is formulated as the one of maximizing the number of primary inputs in the Sc set (or minimizing the number of primary inputs in Sp) It is shown that this analysis can be used in extending single fault test sets in order to achieve a maximal multiple fault coverage. We have presented a procedure for augmenting any single fault test set. An experiment has been carried out on the 74LS181 ALU using twelve single fault test sets. It is shown that different fault classes can be covered using the procedure presented in this paper. A 100% double fault coverage for all the single fault tests is achieved
Keywords :
combinational circuits; fault diagnosis; logic partitioning; logic testing; 74LS181 ALU; combinational circuits; control set; excitation set; maximal multiple fault coverage; partitioning; persistency set; primary inputs; sensitization structure; single fault test sets; Algorithm design and analysis; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Logic testing; Test pattern generators;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580720