DocumentCode
3413270
Title
A 6b 600MHz 10mW ADC array in digital 90nm CMOS
Author
Draxelmayr, D.
Author_Institution
Infineon Design Centers, Villach, Austria
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
264
Abstract
A 6b converter array operates at a 600MHz clock frequency with input signals up to 600MHz and only 10mW power consumption. The array consists of 8 interleaved successive approximation converters implemented in a 90nm digital CMOS technology.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; high-speed integrated circuits; low-power electronics; 10 mW; 600 MHz; 90 nm; ADC array; clock buffer; differential-to-single-ended conversion; digital CMOS; high speed ADC; high throughput; interleaved successive approximation converters; low jitter operation; low power consumption; parallel architecture; Capacitors; Clocks; Data acquisition; Energy consumption; Low voltage; Operational amplifiers; Read-write memory; Sampling methods; Switches; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332695
Filename
1332695
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