A new planar stacked technology (PST) for scaled and embedded DRAMs

We report a Planar Stack Technology (PST) suitable for scaling and combining DRAM with logic circuits. Key features of PST technology are retrograde twin well, shallow trench isolation (STI), self-aligned poly plug structure, damascene W bit-line, Ta/sub 2/O/sub 5/ capacitor dielectric and planarized capacitor formation. This new architecture provides planar surfaces for all the lithographic steps and is easy to combine CMP-based backend processes. Although the process margin and electrical performance are proven using full density, 256 M DRAM chip, this technology can be applied to 1 G bit DRAM and beyond with simple photo lithographic scaling.