240 nm pitch 4 GDRAM array MOSFET technologies with X-ray lithography

This paper describes 240 nm pitch array MOSFET technologies which realize 0.1152 /spl mu/m/sup 2/ cell size for 4 GDRAM. Main features of the array MOSFET are (1) 120 nm line and spaces (L/S) Gate, (2) L/S isolation, (3) Self Aligned Contact (SAG) at 120 nm wide gate-gate space, and (4) 40 nm shallow junction under the SAC plug. X-ray lithography is used for ultra fine patterning and 200 nm pitch (100 nm L/S) active area array is demonstrated. A 120 nm isolation is realized using shallow trench isolation (STI) whose depth is 200 nm. In-situ phosphorus (P) doped poly-silicon is used for SAC plug to make a contact at 120 nm gate space. The shallow junction of 40 nm depth, which suppresses Vth roll-off, is formed by P diffusion from the plug. These technologies can achieve cell area of 0.1152 /spl mu/m/sup 2/ (8F/sup 2/), for 4 GDRAM.