Title :
An algorithm and architecture for the parallel solution of systems of linear equations
Author :
Wilburn, Vincent C. ; Ko, Hak-Lim ; Alexander, Winser E.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
The paper evaluates a paradigm for the efficient utilization of commercially available processors to implement serial algorithms on a parallel architecture. We present an architecture based on this paradigm as well as an algorithm for the parallel solution of a nonhomogeneous system of linear equations with constant coefficients. Major advantages stem from its systolic-like array structure and the versatility of fully programmable processor elements. The method uses a Givens rotation implementation of the well known QR factorization. Unlike other direct methods of factorization followed by backsubstitution, this implementation of the algorithm avoids the backsubstitution bottleneck. The computational complexity of this feedforward direct method of solving nonsingular systems of linear equations is similar to that of QR matrix factorization. Due to the programmability of the processor in the array, the mapping of this algorithm extends to an entire family of algorithms. We map this family of algorithms onto the novel architecture and present a comprehensive performance analysis. Performance results identify the algorithm/architecture combination as a cost effective, efficient method which exhibits speedup that is directly proportional to the number of processors used
Keywords :
computational complexity; feedforward; matrix algebra; parallel architectures; performance evaluation; software performance evaluation; Givens rotation implementation; QR factorization; algorithm mapping; computational complexity; constant coefficients; efficient processor utilisation; feedforward direct method; fully programmable processor elements; linear equation systems; nonsingular systems; parallel architecture; parallel solution; performance analysis; serial algorithms; speedup; systolic-like array structure; Computer architecture; Concurrent computing; Digital signal processing; Distributed computing; Equations; Finite impulse response filter; High performance computing; Linear systems; Parallel architectures; Signal processing algorithms;
Conference_Titel :
Computers and Communications, 1996., Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-3255-5
DOI :
10.1109/PCCC.1996.493662