Performance analysis of internally unbuffered large scale ATM switch with bursty traffic

The authors consider a three-stage switching configuration with no internal buffers, i.e., bufferless switches are used at the first and second stages, and output buffered switches at the third stage. Short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on the performance of the bufferless switches used at the first two stages. A four-stage switching configuration with traffic distributors added at the first stage is proposed. This switch provides more paths between a pair of input and output ports than the three-stage configuration. Some schemes for distributing cells are compared. It is shown that the distributor successfully reduces cell loss probability due to bursty traffic by splitting incoming cells into several switching modules