Advanced integration technology for a highly scalable SOI DRAM with SOC (Silicon-On-Capacitors)

Author

Il-Kwon Kim ; Woo-Tag Kang ; Joon-Hee Lee ; Sunil Yu ; Sang-Cheol Lee ; Kyehee Yeom ; Yun-Gi Kim ; Duck-Hyung Lee ; Giho Cha ; Byoung Hun Lee ; Sang-In Lee ; Kyu-Charn Park ; Tae-Earn Shim ; Chang-Gyu Hwang

Author_Institution

Technol. Dev. Center, Samsung Electron. Co. Ltd., Yongin, South Korea

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

605

Lastpage

608

Abstract

A fully planarized 16 Mb SOI DRAM has been successfully fabricated featuring pattern-bonded SOI (PBSOI), CMP processes, STI (Shallow Trench Isolation) and the silicon-on-capacitor (SOC) structure with 0.3 um technology using i-line lithography. The floating body effects of cell and peripheral SOI transistors are suppressed by the LIF (Local Implantation post Field oxidation) and halo implantation. The fully planarized process with SOC structure is established for multi-gigabit DRAM and embedded memory devices.

Keywords

DRAM chips; integrated circuit technology; silicon-on-insulator; 0.3 micron; 16 Mbit; CMP processing; Si; embedded memory device; floating body effect; halo implantation; i-line lithography; integration technology; local implantation post field oxidation; pattern-bonded SOI; planarization; scalable SOI DRAM; shallow trench isolation; silicon-on-capacitors; Boron; Contact resistance; Degradation; Isolation technology; Lithography; Oxidation; Random access memory; Research and development; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.554056

Filename

554056