Testability controlled physical design of vertically stacked integrated circuits

Author

Reber, Martin ; Kirsch, Armin

Author_Institution

Inst. for Electron., Kaiserslautern Univ., Germany

fYear

1995

fDate

18-22 Sep 1995

Firstpage

249

Lastpage

252

Abstract

Vertical integration technology is expected to provide several advantages, such as high packaging density, parallel processing, high speed operation and an improved reliability. Basic design aspects for vertically stacked integrated circuits are discussed in this paper. A novel partitioning method for vertically stacked integrated circuits (VIC) will be proposed which generates testable circuit partitions. Generated circuit layouts of partitioned MCNC benchmark circuits demonstrate the superiority of 3-D circuit layouts over planar circuit layouts especially for increased circuit sizes

Keywords

application specific integrated circuits; circuit layout CAD; circuit optimisation; design for testability; integrated circuit design; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; logic CAD; logic partitioning; 3D circuit layouts; MCNC benchmark circuits; circuit layouts; circuit sizes; design aspects; high speed operation; packaging density; parallel processing; partitioning method; reliability; testability controlled physical design; testable circuit partitions; vertically stacked integrated circuits; Assembly; Circuit testing; Design optimization; Hardware; Integrated circuit technology; Integrated circuit testing; Observability; Performance evaluation; Registers; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580725

Filename

580725