A 400 mW 50-380 MHz CMOS programmable clock recovery circuit

A high-speed programmable phase-locked loop (PLL) for clock extraction and is presented. This circuit has been manufactured in a 0.8 um CMOS process. The programmable clock recovery PLL can recover a clock from NRZ random data up to 380 Mb/s at which the power consumption is 400 mW from a single 5 volt supply. The chip requires only an external standard crystal to work. Typical performance yields an output clock with peak-to-peak jitter of 6 degree for random data input at 380 Mb/s