Title :
A 400 mW 50-380 MHz CMOS programmable clock recovery circuit
Author :
Larsson, Patrik ; Lee, Jiunn Yih
Author_Institution :
Electron. Res. & Service Organ., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
A high-speed programmable phase-locked loop (PLL) for clock extraction and is presented. This circuit has been manufactured in a 0.8 um CMOS process. The programmable clock recovery PLL can recover a clock from NRZ random data up to 380 Mb/s at which the power consumption is 400 mW from a single 5 volt supply. The chip requires only an external standard crystal to work. Typical performance yields an output clock with peak-to-peak jitter of 6 degree for random data input at 380 Mb/s
Keywords :
CMOS digital integrated circuits; clocks; digital phase locked loops; jitter; 0.8 micron; 380 MHz; 380 Mbit/s; 400 mW; 5 V; CMOS programmable clock recovery circuit; NRZ random data; external standard crystal; high-speed phase-locked loop; peak-to-peak jitter; power consumption; Circuits; Clocks; Data mining; Frequency locked loops; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Programmable control; Voltage-controlled oscillators;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580730
