Title :
3D GIPER: global interconnect parameter extractor for full-chip global critical path analysis
Author :
Oh, S.Y. ; Okasaki, K. ; Moll, J. ; Nakagawa, O.S. ; Rahmat, K. ; Chang, N. ; Hu, D. ; Chow, J. ; Young, T. ; Ho, W.
Author_Institution :
ULSI Res. Lab., Hewlett-Packard Co., Palo Alto, CA, USA
Abstract :
A 3D Global Interconnect Parameter ExtractoR (GIPER) has been developed to provide a practical extraction tool for the full-chip global critical path analysis. It extracts the interconnect parameters (R,C) of a typical global interconnect within several minutes per net on a HP 9000/755 workstation within 5% accuracy compared to full 3D numerical simulations.
Keywords :
circuit layout CAD; critical path analysis; integrated circuit interconnections; integrated circuit layout; 3D GIPER; HP 9000/755 workstation; full-chip global critical path analysis; global interconnect parameter extractor; Capacitance; Clocks; Frequency; Geometry; Integrated circuit interconnections; Libraries; Numerical simulation; Parameter extraction; Routing; Solid modeling;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.554058
