DocumentCode
341364
Title
An analogue multilayer perceptron circuit with on-chip training
Author
Foruzandeh, B. ; Quigley, S.F.
Author_Institution
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Volume
5
fYear
1999
fDate
1999
Firstpage
395
Abstract
This paper reports on the design of a compact CMOS analogue VLSI multilayer perceptron (MLP) with a novel on-chip control circuit that implements the weight perturbation learning rule. A demonstrator chip has been fabricated and tested to establish the correctness of the circuits
Keywords
CMOS analogue integrated circuits; VLSI; analogue processing circuits; feedforward neural nets; learning (artificial intelligence); multilayer perceptrons; neural chips; CMOS analogue VLSI MLP; analogue multilayer perceptron circuit; onchip control circuit; onchip training; weight perturbation learning rule; Analog computers; CMOS analog integrated circuits; Circuit testing; Computer errors; Design engineering; Error correction; Mean square error methods; Multilayer perceptrons; Neural network hardware; Neural networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.777592
Filename
777592
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