DocumentCode
3413699
Title
Single chip array processor for high performance design error simulation
Author
Kang, Sungho ; Szygenda, S.A.
Author_Institution
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
fYear
1995
fDate
18-22 Sep 1995
Firstpage
338
Lastpage
341
Abstract
This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed
Keywords
circuit analysis computing; digital simulation; errors; parallel algorithms; parallel architectures; special purpose computers; high performance accelerator; high performance design error simulation; high speed simulation; massively parallel array processor; single chip array processor; Analytical models; Circuit simulation; Computational modeling; Computer architecture; Computer errors; Computer simulation; Concurrent computing; Costs; Hardware; Logic;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location
Austin, TX
ISSN
1063-0988
Print_ISBN
0-7803-2707-1
Type
conf
DOI
10.1109/ASIC.1995.580744
Filename
580744
Link To Document