Chaotic generation of PN sequences: a VLSI implementation

Generation of repeatable pseudo-random sequences with chaotic analog electronics is not feasible using standard circuit topologies. Component variation caused by imperfect fabrication causes the same divergence of output sequences as does varying initial conditions. By quantizing the output of a simple chaotic difference equation and using delayed feedback, we are able to construct a circuit which has properties both of randomness and repeatability. Simulation results show sequence lengths in excess of 10000 bits with cross correlations less than 0.02 for our architecture. The system has been implemented using AMI 1.2 μm CMOS technology, and digitally using AMD MACH complex programmable logic devices (CPLDs). Circuit measurements are in agreement with our theoretical findings