Finite state machine extraction from hardware description languages

This paper present technique to extract a finite state machine (FSM) description from sequential behaviors describe in hardware description languages (HDL). Sequential behaviors can be described with an explicit state register which is assigned next state values. The extraction of these explicit sequential behaviors is based on the extraction of (value, condition) pairs from directed acyclic graphs. In addition, hardware description languages provide constructs, such as wait statements, that permit the descriptions of implicit sequential behaviors. Implicit sequential behaviors are extracted by a path-directed technique applied on a directed, cyclic, non-series/parallel control flow graph with embedded data flow graphs