Notice of Violation of IEEE Publication PrinciplesA 160-2550MHz CMOS active clock deskewing PLL using analog phase interpolation

Notice of Violation of IEEE Publication Principles

"A 160-2550MHz CMOS active clock deskewing PLL using analog phase interpolation"
by Maxim, A.
in the Proceedings of the 2004 IEEE International Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC.
15-19 Feb. 2004 Vol.1, Page(s):346 - 532

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.An active clock-deskewing PLL uses analog-phase interpolation to generate the local shifted clocks. It provides a uniform and process independent phase-step over the entire deskew range, and a zero-latency phase shift to speed-up the deskewing process. This 400x800μm/sup 2/ PLL is fabricated in a 0.15μm CMOS process having a frequency range of 160 to 2550MHz, phase step of 2.8°, RMS jitter <1 % T/sub osc/ and draws 60mW from a 1.5V supply.