DocumentCode
3414068
Title
Design and analysis of a jitter-tolerant digital delay-locked-loop based fraction-of-clock delay line
Author
Burnham, J.R. ; Sun, E. ; Chih-Kong Ken Yang
Author_Institution
Stanford Univ., CA, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
352
Abstract
A digital DLL-based fraction-of-clock delay line is described. It uses a combination of scaling and phase-detector window alignment to improve jitter tolerance and loop stability without requiring a loop filter or reducing tracking bandwidth.
Keywords
DRAM chips; clocks; delay lock loops; high-speed integrated circuits; phase detectors; timing jitter; DDR SDRAM interface; Simulink models; fraction-of-clock delay line; high jitter tolerance; high-speed interfaces; jitter-tolerant digital delay-locked-loop; loop stability; memory interface block; phase-detector window alignment; scaling alignment; standard cell process; worst-case delay variation; Bandwidth; Circuits; Clocks; Crosstalk; Delay lines; Detectors; Filters; Jitter; Phase detection; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332739
Filename
1332739
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