A comparison of architectures for a programmable fuzzy logic chip

Author

Lund, T. ; Torralba, A. ; Carvajal, R.G. ; Ramirez-Angulo, J.

Author_Institution

Fac. of Inf. Sci. & Eng., Canberra Univ., Canberra, ACT, Australia

Volume

5

fYear

1999

fDate

1999

Firstpage

623

Abstract

Three possible architectures for a programmable fuzzy logic chip are proposed and examined in terms of their implications for implementation. The capabilities of each architecture in terms of number of inputs and outputs usable, and the number of membership functions available for each of these, the size of the possible rule base, and the versatility and programmability of the design, are weighed against the chip area required, the likely power consumption, and the accuracy and throughput

Keywords

analogue processing circuits; field programmable gate arrays; fuzzy logic; mixed analogue-digital integrated circuits; programmable circuits; programmable logic arrays; random-access storage; ASIC; FPGA style; MIN array; PAL configuration; RAM configuration; accuracy; architectures comparison; chip area requirement; membership functions; power consumption; programmability; programmable fuzzy logic chip; rule base size; throughput; Australia; Circuit testing; Computer architecture; Energy consumption; Field programmable gate arrays; Fuzzy control; Fuzzy logic; Integrated circuit interconnections; Prototypes; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777649

Filename

777649