Author_Institution :
Dept. of Comput. Sci. & Electr. Eng., Vermont Univ., Burlington, VT, USA
Abstract :
In this paper, we study wide-sense nonblocking conditions under packing strategy for the three-stage Clos network, or v(m, n, r) network. Wide-sense nonblocking networks are generally believed to have lower network cost than strictly nonblocking networks. However, the analysis for the wide-sense nonblocking conditions is usually more difficult. Moore proved that a v(m, n, 2) network is nonblocking under packing strategy if the number of middle stage switches m⩾[3 /2n]. This result has been widely cited in the literature, and is even considered as the wide-sense nonblocking condition under packing strategy for the general v(m, n, r) networks in some papers. In fact, it is still not known that whether the condition m⩾[3/2n] holds for v(m, n, r) networks when r⩾3. In this paper, we introduce a systematic approach to the analysis of wide-sense nonblocking conditions under packing strategy for general v(m, n, r) networks with any r values. We first translate the problem of finding the necessary and sufficient nonblocking conditions for v(m, n, r) networks to a set of linear programming problems. We then solve this special type of linear programming problems and obtain an elegant dosed form optimum solution. We prove that the necessary and sufficient condition for a v(m, n, r) network to be nonblocking under packing strategy is m⩾[(2-1/F2r-1)n] where F2r-1 is the Fibonaaci number. We believe that the systematic approach developed in this paper can be used for analyzing other wide-sense nonblocking control strategies as well
Keywords :
linear programming; multiprocessor interconnection networks; Fibonaaci number; linear programming; necessary and sufficient nonblocking conditions; packing strategy; wide-sense nonblocking Clos networks; wide-sense nonblocking conditions; Communication switching; Communication system control; Computer science; Control systems; Costs; Joining processes; Linear programming; Routing; Sufficient conditions; Switches;