DocumentCode
3414196
Title
A 13b 1.1 MHz oversampled DAC with semidigital reconstruction filtering
Author
Francese, Pier Andrea ; Qiuting Huang
Author_Institution
Integrated Syst. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
370
Abstract
A 1b and 5b digital ΣΔ modulator cascade sharpens noise shaping while maintaining linearity. A semi-digital SC FIR reconstruction filter combined with an IIR SC/RC filter reduce clock harmonics below the ADSL spurious emission mask. The 0.18μm 1P6M CMOS chip achieves 80dB SFDR, 78dB SNR and 74dB SNDR within 1.1MHz.
Keywords
CMOS integrated circuits; FIR filters; IIR filters; digital-analogue conversion; sigma-delta modulation; signal sampling; switched capacitor filters; 1.1 MHz; ADSL spurious emission mask; CMOS chip; IIR filter; SC FIR reconstruction filter; broadband performance; clock harmonics; digital sigma-delta modulator cascade; oversampled DAC; semidigital reconstruction filtering; steep attenuation; Bandwidth; Calibration; Capacitors; Cutoff frequency; Digital modulation; Filtering; Finite impulse response filter; Linearity; Nonlinear filters; Quantization;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332748
Filename
1332748
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