Title :
A load-adaptive, low switching-noise data output buffer
Author :
Lee, Seung-Wook ; Shim, Daeyun ; Jung, Yeon-Jae ; Lee, Dong-Yun ; Kim, Chang-Hyun ; Kim, Wonchan
Author_Institution :
Sch. of Electr. Eng., Seoul Nat. Univ., South Korea
Abstract :
This paper describes a data output buffer which shows a reduced switching noise over wide-range of loading conditions. The proposed output buffer employs load-adaptive circuitry to achieve bounded delay regardless of loading condition. For that purpose, a load monitoring circuit is embedded in the output buffer. The adaptive control of driving current enables the switching noise to be kept at a minimum value. The experimental chip with a 0.61 μm CMOS technology shows a reduced switching noise level, 15%~35% of conventional buffer while the transition time is bounded within 7 ns for loading capacitance up to 100 pF
Keywords :
CMOS memory circuits; buffer circuits; capacitance; delays; integrated circuit noise; 0.6 micron; 7 ns; CMOS technology; bounded delay; data output buffer; driving current; load monitoring circuit; load-adaptive circuitry; loading capacitance; loading conditions; memory circuits; noise level; switching noise; transition time; Adaptive control; CMOS technology; Capacitance; Circuit noise; Delay; Integrated circuit interconnections; Monitoring; Noise level; Noise reduction; Timing;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777800
