Title :
Minimizing switchings of the function units through binding for low power
Author :
Kumar, Ashok ; Bayoumi, Magdy ; Cherabuddi, Raghava
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
This paper considers minimizing the switchings of the function units in high-level synthesis. Switching activities on the function units are gathered through profiling the data-flow graph of the design at hand. Several thousands of random input streams are generated and used for such profiling. A genetic algorithm is employed for creation of a wide variety of random input patterns which are critical to measuring the switching activities. The switching activities are obtained and stored in a matrix. The problem of binding the function units for low power is then formulated and solved by using the proposed method. Based on the simulations, a power saving of 8%-24%, due to reduced switchings, is indicated for the considered standard benchmarks
Keywords :
CMOS digital integrated circuits; VLSI; data flow graphs; genetic algorithms; high level synthesis; low-power electronics; binding; data-flow graph; function units; genetic algorithm; high-level synthesis; low power; power saving; random input patterns; standard benchmarks; Circuits; Energy consumption; Genetic algorithms; High level synthesis; Portable computers; Power dissipation; Power generation; Processor scheduling; Random number generation; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777807