A fully integrated 13 GHz ΔΣ fractional-n PLL in 0.13 μm CMOS

Author

Tiebout, Marc ; Sandner, C. ; Wohlmuth, H.D. ; Da Dalt, Nicola ; Thaller, E.

Author_Institution

Corporate Res., Infineon Technol. AG, Munich, Germany

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

386

Abstract

A 13 GHz PLL designed for future WLAN systems in the 17 GHz ISM band includes a differentially tuned LC VCO, IQ-divider, 212-217 low power multi-modulus prescaler, differential phase-frequency detector, charge pump with loop filter, and a 2nd-order noise-shaping ΔΣ modulator. Total power consumption is 60 mW from a 1.5 V supply.

Keywords

CMOS integrated circuits; circuit tuning; delta-sigma modulation; differential detection; frequency dividers; integrated circuit measurement; integrated circuit noise; low-power electronics; phase locked loops; prescalers; voltage-controlled oscillators; wireless LAN; 0.13 micron; 1.5 V; 13 GHz; 17 GHz; 60 mW; CMOS; IQ-divider; ISM band; WLAN systems; charge pump; differential phase-frequency detector; differentially tuned LC VCO; fully integrated ΔΣ fractional-n PLL; loop filter; low power multi-modulus prescaler; power consumption; second-order noise-shaping delta-sigma modulator; Charge pumps; Delta modulation; Filters; Noise shaping; Phase detection; Phase frequency detector; Phase locked loops; Phase modulation; Voltage-controlled oscillators; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332756

Filename

1332756