Device level based cell modeling for fast power estimation

In this work, a method for fast power estimation in complex digital circuits is presented. Properties like delay and power consumption of a circuits basic cells are extracted precisely by circuit level simulations. The cell model then includes delay and power consumption values for all possible transitions at the cell inputs. The total power consumption is finally determined by logic simulation at higher architectural levels. The cell model also includes the glitching behavior at the outputs resulting from different path delays inside a cell. It is shown experimentally that this delay model, including glitches generated by the basic cells, leads to good power estimation results of complex circuits within an accuracy of 8% in the worst case and needs 4 and 2 orders of magnitude less simulation time than SPICE and PowerMill respectively