• DocumentCode
    341438
  • Title

    On-line IDDQ fault testing for CMOS/BiCMOS logic families

  • Author

    Raahernifar, K. ; Ahmadi, Majid

  • Author_Institution
    Dept. of Electr. Eng., Windsor Univ., Ont., Canada
  • Volume
    1
  • fYear
    1999
  • fDate
    36342
  • Firstpage
    105
  • Abstract
    This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause IDDQ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated
  • Keywords
    BiCMOS logic circuits; delays; design for testability; fault diagnosis; integrated circuit testing; logic testing; CMOS/BiCMOS logic families; IDDQ fault testing; circuit modification; delay faults; design-for-testability technique; normal mode; open defects; simulation-based fault characterization study; stuck-open faults; BiCMOS integrated circuits; Bipolar transistors; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic testing; MOSFETs; Resistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-7803-5471-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1999.777816
  • Filename
    777816
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=341438