VLSI implementation of a multicast ATM switch

Author

Chang, Robert C. ; Kuo, Lung-Chih ; Hsieh, Chih-Yuan

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

Volume

1

fYear

1999

fDate

36342

Firstpage

129

Abstract

In this paper, VLSI design of a multicast ATM switch controller is presented. The ATM switch system is based on the shared multibuffer architecture. The cyclic queue algorithm is used at the address queues to increase the throughput, and no memory speed up is needed. By employing the multicast queue and dynamic multicast scheme, multicast functions can be efficiently carried out and the hardware complexity is reduced. The 8×8 switch is designed to handle the OC-12 (622 Mbps) transmission rate. The switch controller is designed by using a 0.6 μm single-poly triple-metal CMOS technology. Simulation results show that the chip can correctly operate at 40 MHz

Keywords

CMOS digital integrated circuits; VLSI; asynchronous transfer mode; multicast communication; 0.6 micron; 40 MHz; 622 Mbit/s; ATM switch controller; VLSI implementation; cyclic queue algorithm; dynamic multicast scheme; hardware complexity; multicast ATM switch; shared multibuffer architecture; single-poly triple-metal CMOS technology; Asynchronous transfer mode; CMOS technology; Centralized control; Circuits; Hardware; Multicast algorithms; Routing; Switches; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777821

Filename

777821