DocumentCode
341446
Title
Cost-effective low-power architectures of video coding systems
Author
Chen, Jie ; Liu, K. J Ray
Author_Institution
Bell Labs., Lucent Technol., Murray Hill, NJ, USA
Volume
1
fYear
1999
fDate
36342
Firstpage
153
Abstract
A new low-power design technique, multirate, has been used along with other methods such as look-ahead and pipelining in designing the cost-effective low-power architectures of video coding systems. We demonstrate both low-power and high-speed can be accomplished at algorithm/architecture level. Based on the calculation and simulation results, the design can achieve significant power saving in the range of 60%-80% or speedup factor of two depending on the needs of users
Keywords
VLSI; low-power electronics; motion estimation; multimedia communication; pipeline processing; video coding; architecture level; look-ahead; low-power architectures; multirate technique; pipelining; power saving; video coding systems; Algorithm design and analysis; Costs; Discrete cosine transforms; Fabrication; Motion estimation; Pipeline processing; Silicon; Very large scale integration; Video coding; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.777826
Filename
777826
Link To Document