Design and implementation of a 118 MHz 2D DCT processor

Frequency analysis using the discrete cosine transforms (DCT) is an obvious choice for digital signal and image processing domain. This paper describes the implementation of 2D-DCT processor for the synchronous design in a Xilinx VertexIV FPGA device. The DCT core architecture is based on the distributed arithmetic. The total dynamic power of the processor is 371 mW, in an operating frequency of 118.2 MHz is achieved. The paper presents the trade-offs involved in designing the architecture, the design for performance issues and the possibilities for future development.