Power consumption of a 2´s complement adder minimized by effective dynamic data ranges

Typically, two´s complement is chosen to represent numbers since arithmetic operations of addition and subtraction are easy to perform. However, due to sign extension, an arithmetic operation for small dynamic data ranges may require switching power in the entire word length. Herein, we develop a two´s complement adder with the dynamic-range determination and sign-extension units to reduce power consumption. According to the actual data range by minimizing sign-extension bits, only partial functional blocks of an adder are active to generate a final result of which sign bit is then extended to match the original word length. Experimental results demonstrate that our 32-bit carry-lookahead adder has 22.9% power reduction than the conventional one while dynamic ranges of input data are the Gaussian distribution with a mean of 16 bits and a standard deviation of 8 bits