DocumentCode
341471
Title
An efficient data path synthesis algorithm for behavioral-level power optimization
Author
Chaeryung Park ; Park, Chaeryung ; Liu, C.L.
Author_Institution
Synopsys Inc., Mountain View, CA, USA
Volume
1
fYear
1999
fDate
36342
Firstpage
294
Abstract
This paper presents a new data path synthesis algorithm which solves two important design problems: scheduling and allocation with power minimization as a key design objective. Based on the observations found in prior work on synthesis for low power we derive an integer programming formulation for solving the problem. We then develop a stepwise approximation algorithm utilizing the formulation to carry out the scheduling and allocation in an integrated fashion. Our experimentation results show that the algorithm is quite effective, producing designs with significant savings in power consumption
Keywords
VLSI; circuit optimisation; hardware description languages; high level synthesis; integer programming; integrated circuit design; low-power electronics; scheduling; allocation; behavioral-level power optimization; data path synthesis algorithm; integer programming formulation; power consumption; scheduling; stepwise approximation algorithm; Algorithm design and analysis; Circuits; Clocks; Computer science; Energy consumption; Flow graphs; Linear programming; Processor scheduling; Scheduling algorithm; Turning;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location
Orlando, FL
Print_ISBN
0-7803-5471-0
Type
conf
DOI
10.1109/ISCAS.1999.777861
Filename
777861
Link To Document