Title :
Fast timing driven placement using tabu search
Author :
Emmert, John M. ; Bhatia, Dinesh
Author_Institution :
ECECS Dept., Cincinnati Univ., OH, USA
Abstract :
Search based placement of modules is an important problem in VLSI design. It is desired that the search should converge very quickly to a good quality solution. In this paper we have investigated the applicability of the tabu search based optimization technique applied to timing driven placement of modules on regular two-dimensional arrays. Our goal is to speed up the placement process. We have designed a two-step placement strategy that provides quality results in an extremely short execution time. We demonstrate the applicability of our technique by placing several circuits on the Xilinx XC4000 series FPGAs. We compare our results to a simulated annealing based algorithm with similar cost function and to commercial CAE tools. We show significant speedup relative to convergence to good solutions when compared to simulated annealing. Similarly we show an average execution time speedup of 20 with no impact on quality of results when compared to commercial tools
Keywords :
VLSI; circuit layout CAD; circuit optimisation; field programmable gate arrays; integrated circuit layout; logic CAD; logic arrays; simulated annealing; timing; FPGAs; VLSI design; Xilinx XC4000 series; cost function; execution time; optimization technique; regular two-dimensional arrays; simulated annealing; tabu search; timing driven placement; Circuits; Computer aided engineering; Cost function; Design automation; Field programmable gate arrays; Laboratories; Process design; Simulated annealing; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777863
