Title :
Scheduling with multiple voltages under resource constraints
Author :
Sarrafzadeh, M. ; Raje, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
Abstract :
This paper presents a low power design technique at the behavioral synthesis stage. Multiple voltages are used to run the functional units. The input to our problem is an unscheduled data flow graph with a timing constraint and a resource constraint. The resource constraint is given as the number and type of each of the functional units to be used and the supply voltage at which it would run. The goal is to maximize the number of operation nodes in the flow graph that are mapped to functional units running at the lower supply voltage while still satisfying the timing constraints. We propose two algorithms, one is a dynamic programing algorithm that gives optimal (i.e., minimum power consumption) results for the two-voltage problem; the second, is a heuristic geometric scheduling algorithm. The experimental results for some high-level synthesis benchmarks show 13% to 32% reduction in the power consumption
Keywords :
circuit CAD; dynamic programming; flow graphs; high level synthesis; integrated circuit design; low-power electronics; scheduling; timing; CAD; behavioral synthesis stage; dynamic programing algorithm; functional units; heuristic geometric scheduling algorithm; high-level synthesis benchmarks; low power design technique; minimum power consumption; multiple voltages; power consumption reduction; resource constraints; timing constraint; two-voltage problem; unscheduled data flow graph; Flow graphs; Hardware; Logic; Minimization; Power engineering computing; Processor scheduling; Scheduling algorithm; Throughput; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777875
