Title :
A 15 b 20 MS/s CMOS pipelined ADC with digital background calibration
Author :
Hung-Chih Liu ; Zwei-Mei Lee ; Jieh-Tsorng Wu
Author_Institution :
Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Abstract :
A 15 b 20 MS/s CMOS pipelined ADC is fabricated in a 0.18 μm dual-gate CMOS technology and achieves 94 dB SFDR and 74 dB SNDR for a 8 MHz input. Digital calibration can proceed continuously in the background to maintain the ADC resolution. The chip occupies an area of 3.3×3.4 mm2 and dissipates 235 mW with 1.8 V and 3.3 V dual supplies.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; integrated circuit measurement; pipeline processing; signal resolution; 0.18 micron; 1.8 V; 15 bit; 235 mW; 3.3 V; 3.3 mm; 3.4 mm; 8 MHz; ADC resolution; CMOS pipelined ADC; SFDR; SNDR; chip area; continuous background calibration; digital background calibration; dual supplies; dual-gate CMOS technology; Analog-digital conversion; CMOS technology; Calibration; Capacitors; Clocks; Linearity; Low pass filters; Pipelines; Sampling methods; Silicon;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332790
