Design procedure based on VHDL language transformations

Automated hardware synthesis starting from the register transfer level (RT-level) VHDL description is well established. However, starting the design on a higher abstraction level than the RT-level is one of the major problems within the VHDL based system synthesis. We present a novel design procedure called SYLANT (Synthesis based on Language Transformations), which uses the methodology of high-level synthesis. It starts from the abstract functional model and produces an RT-level description through successive language transformations. The biggest advantage of this method is that no other description technique than the standard VHDL is considered. The intermediate VHDL code is accessible to the designer, the circuit model can be simulated after each design step. Different algorithms can be implemented for any step, depending on the applied technology dependent information and various RT-level architectures can be obtained. The output VHDL format is suitable to continue the design flow with RT-level based synthesis tools