Title :
A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 μm CMOS with 99 dB SFDR
Author :
Yun Chiu ; Gray, P.R. ; Nikolic, B.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm2 in 0.18 μm CMOS and dissipates 112 mW.
Keywords :
CMOS integrated circuits; analogue-digital conversion; capacitors; error analysis; integrated circuit measurement; pipeline processing; 0.18 micron; 1 MHz; 1.8 V; 112 mW; 14 bit; 5.1 MHz; CMOS pipelined ADC; DNL; INL; SFDR; SNDR; analog input; calibration; chip area; nested CMOS gain boosting; passive capacitor error-averaging; power dissipation; signal frequencies; trimming; Boosting; CMOS technology; Capacitors; Circuit noise; Frequency; Low voltage; Operational amplifiers; Pipelines; Sampling methods; Signal to noise ratio;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332792
