A Single Chip Implementation of AES Cipher and Whirlpool Hash Function

Advanced Encryption Standard (AES) is adopted as the standard for symmetric key cryptosystem. Hash functions are used as building blocks in various cryptographic applications. Whirlpool is one of the best known hash function reported in the literature. Many hardware based implementations of AES and Whirlpool have been proposed on separate chips. This paper presents an efficient hardware design for the AES and Whirlpool algorithm on a single chip which reduces the overall chip area. The design is implemented in Verilog and synthesized using Xilinx ISE 10.1.