Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability

Modern FPGAs use SRAM-cells to store the programming bits that drive the switching matrices. The area of these SRAM cells can be as large as 40% of the total area. This figure dramatically increases in the case of multicontext FPGAs, where the programming configuration has to be repeated as many times as contexts. This problem is alleviated if the switches that connect an input line to several output lines in each switching block are driven by a decoder. In this case, the number of SRAM cells decreases in O(log), at the cost of routability. This paper shows with experimental results obtained from 175 benchmark circuits that, for usual FPGA parameters, routability losses are small, making the decoder-driven switch (DDS) approach an excellent method for reducing FPGA area by as much as 20%, while preserving routability