Title :
A low complexity Reed-Solomon architecture using the Euclid´s algorithm
Author :
Chang, Hyunman ; Sunwoo, Myung H.
Author_Institution :
Sch. of Electr. & Electron. Eng., Ajou Univ., Suwon, South Korea
Abstract :
This paper describes an efficient pipelined Reed-Solomon (RS) decoder. The proposed RS decoder architecture is based on the Euclid´s algorithm, which can reduce the hardware complexity by more than 16% of existing RS architecture. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 28, i.e. (200, 188), (120, 108), (60, 48), and (40, 28) and can correct up to six errors. We have developed VHDL models and performed logic synthesis using the SYNOPSYS CAD tool. We have used the SAMSUNG 0.6 μm SOG (Sea-of-Gates) cell library (KG75000). The total number of gates is about 31,000 and the proposed RS decoder operates at 40 MHz for the worst case simulations
Keywords :
CMOS digital integrated circuits; Galois fields; Reed-Solomon codes; VLSI; circuit CAD; decoding; digital signal processing chips; error correction codes; logic CAD; pipeline processing; 0.6 micron; 40 MHz; Euclid´s algorithm; Galois field; KG75000; RS decoder architecture; Reed-Solomon architecture; SAMSUNG SOG cell library; SYNOPSYS CAD tool; VHDL models; hardware complexity reduction; logic synthesis; low complexity RS architecture; pipelined Reed-Solomon decoder; sea-of-gates cell library; Decoding; Delay; Error correction; Error correction codes; Frequency domain analysis; Galois fields; HDTV; Hardware; Mobile communication; Reed-Solomon codes;
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
DOI :
10.1109/ISCAS.1999.777941
