Power and signal integrity improvement in ultra high-speed current mode logic

Current mode (ECL) logic has long been the option of choice in those applications requiring logic functions at multigigahertz rates. This trend continues despite the obvious very high static power consumption and small signal swing characterizing this logic. In this work we investigate a simple mechanism for Low-Voltage-Swing Logic (LVSL) to greatly reduce the power requirement of a CML logic subsystem while improving the reliability and signal integrity. For the presented circuits operating at 5 GHz, 50% power reduction is achieved while improving the signal integrity