Dynamic CMOS noise immunity estimation in submicron regime

Author

Kabbani, A. ; Al-Khalili, A.J.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

Volume

1

fYear

1999

fDate

36342

Firstpage

529

Abstract

Noise may limit system performance, or it may push the system to malfunction. Hence a good system design has to take care of the noise problem. This paper addresses this issue and presents models to compute the noise immunity of dynamic CMOS circuits in submicron regime. Our models compute the maximum safe amplitude of a noise pulse in terms of the pulse duration as well as the circuit parameters. Also in these models the mobility degradation and velocity saturation have been taken in account. We have considered the cases where noise pulse is applied to one of the circuit inputs or the clock input. HSPICE simulations confirm the validity of these models

Keywords

CMOS logic circuits; carrier mobility; integrated circuit modelling; integrated circuit noise; logic design; circuit parameters; dynamic CMOS circuits; maximum safe amplitude; mobility degradation; models; noise immunity estimation; pulse duration; submicron regime; velocity saturation; CMOS technology; Circuit noise; Clocks; Degradation; Noise level; Pulse circuits; Semiconductor device modeling; Space vector pulse width modulation; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777945

Filename

777945