DocumentCode
3415177
Title
Output buffer impedance control and noise reduction using a speed-locked loop
Author
Bazes, M.
Author_Institution
Intel, Haifa, Israel
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
486
Abstract
This paper presents a digital speed-locked loop (SLL) which controls the output buffer drive strength in an Ethernet controller chip. The SLL automatically determines the chip speed and adjusts the output buffer drive strength so that buffer impedance and switching noise remain within narrow limits over all process, voltage, and temperature conditions.
Keywords
buffer circuits; circuit feedback; impedance matching; integrated circuit noise; oscillators; Ethernet controller chip; SLL; automatic chip speed detection; digital speed-locked loop; digitally controlled oscillator feedback loop; high-speed output buffers; impedance control; impedance matching; output buffer drive strength control; switching noise reduction; Circuits; Communication cables; Frequency; Impedance matching; Inverters; Noise reduction; Phase locked loops; Temperature control; Temperature distribution; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332806
Filename
1332806
Link To Document