Performance investigation on the reconfigurable Si nanowire schottky barrier transistors

In this paper, the performance of the reconfigurable Si nanowire Schottky barrier transistors (RFETs) is investigated with simulation method. In contrast to conventional Schottky barrier MOSFETs (SB-MOSFETs) and silicon nanowire transistors (Si-NWTs) with metal/silicide as source/drain, the separate two gates in RFETs are located at the two Schottky junctions. Our simulation results show the variable electric characteristics and working principle of the RFETs working as p-/n-type. The RFETs exhibit higher on/off current ratio compared with other Schottky transistors.