DocumentCode
3415370
Title
An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation
Author
Foley, Raymond E. ; Kavanagh, Richard C. ; Marnane, W.P. ; Egan, Michael G.
Author_Institution
Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Ireland
Volume
3
fYear
2005
fDate
6-10 March 2005
Firstpage
1412
Abstract
This paper describes a digital pulsewidth modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.
Keywords
DC-DC power convertors; PWM power convertors; digital control; field programmable gate arrays; power engineering computing; switching convertors; DPWM; FPGA implementation; digital control; digital pulsewidth modulation architecture; frequency calibration method; multioutput pulsewidth modulation scheme; two phase dc-dc buck converter; Counting circuits; Delay; Digital modulation; Field programmable gate arrays; Frequency; Power generation; Pulse modulation; Pulse width modulation; Pulsed power supplies; Space vector pulse width modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth Annual IEEE
Print_ISBN
0-7803-8975-1
Type
conf
DOI
10.1109/APEC.2005.1453214
Filename
1453214
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