DocumentCode
3415417
Title
Stress management for CESL based strained PMOSFET using trench structure
Author
Qian Luo ; Bin Liu ; Qi Yu ; Xiang-zhan Wang ; Jing-chun Li
Author_Institution
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2012
fDate
Oct. 29 2012-Nov. 1 2012
Firstpage
1
Lastpage
3
Abstract
We demonstrate a trench based structure to modulate the stress induced by the contact etch stop layer (CESL) in strained MOSFET. The strained PMOSFETs with gate length varying from 45 nm to 225 nm are simulated to investigate the effects of the trench based structure on channel stress. The calculation results show that, for the device strained by a tensile CESL, the application of such a structure successfully changes the channel state of stress from tensile to compressive. In combination with the conventional strained Si technology, this novel approach provides a solution to enhance the performance of PMOSFET and NMOSFET simultaneously using a single type strained CESL.
Keywords
MOSFET; CESL based strained PMOSFET; NMOSFET; Si; channel state; channel stress; contact etch stop layer; gate length; size 45 nm to 225 nm; strained technology; stress management; trench based structure; Compressive stress; Laboratories; Logic gates; MOSFET circuits; Performance evaluation; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4673-2474-8
Type
conf
DOI
10.1109/ICSICT.2012.6467590
Filename
6467590
Link To Document