Design and IC implementation of an ultra-low-ripple switched-capacitor-based buck dc-dc converter

Author

Han, Jifeng ; Von Jouanne, Annette ; Temes, Gabor C.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA

Volume

3

fYear

2005

fDate

6-10 March 2005

Firstpage

1447

Abstract

A 5 V/1.1 V, 150 mA, ultra-low-ripple, and high-efficiency switched-capacitor (SC) buck converter is presented based on the interleaved discharging (ID) approach. The circuit is designed using the TSMC 0.35 μm process. A novel multiphase PWM generator is also proposed. Simulation and preliminary experimental results show that the output ripple is reduced by a factor of about 3, and the efficiency is improved by 7% under rated load current The ID method provides flexibility in the design optimization of step-down SC dc-dc converters.

Keywords

DC-DC power convertors; PWM power convertors; capacitor switching; discharges (electric); integrated circuits; network topology; optimisation; 0.35 mum; 1.1 V; 150 mA; 5 V; TSMC; buck dc-dc converter; design optimization; interleaved discharging approach; multiphase PWM generator; step-down SC dc-dc converter; ultra-low-ripple switched-capacitor converter; Buck converters; Capacitors; DC-DC power converters; Integrated circuit noise; Pulse width modulation; Semiconductor diodes; Switches; Switching converters; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth Annual IEEE

Print_ISBN

0-7803-8975-1

Type

conf

DOI

10.1109/APEC.2005.1453220

Filename

1453220