DocumentCode
3415519
Title
Rad-Hard 32 nm FinFET Based Inverters
Author
Rathod, S.S. ; Saxena, A.K. ; Dasgupta, S.
Author_Institution
Electron. & Comput. Eng. Dept., Indian Inst. of Technol., Roorkee, India
fYear
2009
fDate
18-20 Dec. 2009
Firstpage
1
Lastpage
4
Abstract
This paper reports a novel circuit level hardening technique that can decrease sensitivity to radiation induced single event upsets in 32 nm FinFET based circuits. Five different types of 32 nm FinFET based inverters are analyzed. Proposed design outperforms over the unhardened circuit when exposed to radiation. This is majorly due to the innovative design technique used to neutralize effect of single event upset without affecting normal operation. Effect of back gate voltage and back gate oxide thickness variation is reported. Results indicate that the proposed design has good hardness to single event upset but has little area and power overheads than the unhardened FinFET based design.
Keywords
MOSFET circuits; invertors; radiation hardening (electronics); FinFET based circuits; back gate oxide thickness; back gate voltage; circuit level hardening; innovative design technique; inverters; single event upset; unhardened circuit; Circuits; Doping; Electrostatics; FinFETs; Inverters; Radiation hardening; Silicon; Single event upset; Space technology; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
India Conference (INDICON), 2009 Annual IEEE
Conference_Location
Gujarat
Print_ISBN
978-1-4244-4858-6
Electronic_ISBN
978-1-4244-4859-3
Type
conf
DOI
10.1109/INDCON.2009.5409457
Filename
5409457
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