DocumentCode :
3415572
Title :
Streamlining HW-SW architecture development, verification and validation
Author :
Hasan, Q. ; Wendong Hu ; Ankolekar, P. ; Pan Lijun
Author_Institution :
Syst. & Software Eng., Spansion Inc., CA, USA
fYear :
2012
fDate :
Oct. 29 2012-Nov. 1 2012
Firstpage :
1
Lastpage :
3
Abstract :
The lack of code reuse in state-of-the-art verification methodologies results in long verification cycles. In this paper we present a new approach that structures the design/verification environment into 3 elements to ensure 100% reuse of verification codes across design phases: design abstraction, the abstraction-independent driver, and software applications on top of the driver. Through a real-world design project, we confirm an expected ~35% saving in verification time over the classic methodology.
Keywords :
hardware-software codesign; integrated circuit design; abstraction-independent driver; code reuse; design abstraction; design phases; design/verification environment; software applications; state-of-the-art verification methodologies; streamlining HW-SW architecture development; validation; Field programmable gate arrays; Hardware design languages; Measurement; Registers; Software; Time varying systems; Unified modeling language;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4673-2474-8
Type :
conf
DOI :
10.1109/ICSICT.2012.6467602
Filename :
6467602
Link To Document :
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