Conflict-free access to multiple single-ported register files

Presents a novel static algorithm for mapping values to multiple register files. The algorithm is based on the edge-coloring of a bipartite graph. It at lows the migration of values among the register files to keep the number of RAMs as small as possible. By comparison with the register file design used in the Cydra 5 mini-supercomputer, our approach substantially reduces the number of RAMs. This reduction actually grows with the issue rate. For a system with an issue rate of 6 instructions per cycle, the cost (gate count) of the register files are already cut by half. On a numerical workload like the Livermore Loops, both designs achieve roughly the same performance