Title :
The impact of timing on linearizability in counting networks
Author :
Mavronicolas, Marios ; Papatriantafilou, Marina ; Tsigas, Philippas
Author_Institution :
Dept. of Comput. Sci., Cyprus Univ., Nicosia, Cyprus
Abstract :
Counting networks form a new class of distributed, low-contention data structures made up of interconnected balancers, and are suitable for solving a variety of multiprocessor synchronization problems that can be expressed as counting problems. A linearizable counting network guarantees that the order of the values it returns respects the real-time order they were requested. Linearizability significantly raises the capabilities of the network, but at a possible price in network size or synchronization support. In this paper, we further pursue the systematic study of the impact of timing on linearizability for counting networks, along a research line initiated by Lynch et al. (1996). We consider two basic timing models: the instantaneous balancer model, in which the transition of a token from an input to an output port of a balancer is modeled as an instantaneous event, and the periodic balancer model, where balancers send out tokens at a fixed rate. We also consider lower and upper bounds on the delays incurred by wires connecting the balancers. We present necessary and sufficient conditions for linearizability in the form of precise inequalities that involve timing parameters and identify structural parameters of the counting network, which may be of more general interest. Our results significantly extend and strengthen previous impossibility and possibility results on linearizability in counting networks (Herlihy et al., 1990; Lynch et al., 1996)
Keywords :
counting circuits; delays; directed graphs; linearisation techniques; multiprocessor interconnection networks; parallel algorithms; synchronisation; timing; tree data structures; counting networks; delays; distributed low-contention data structures; impossibility results; instantaneous balancer model; instantaneous event; interconnected balancers; linearizability; lower bound; multiprocessor synchronization problems; necessary conditions; network size; periodic balancer model; possibility results; precise inequalities; real-time order; structural parameters; sufficient conditions; timing; token transition; upper bound; wires; Algorithm design and analysis; Computer science; Counting circuits; Data structures; Delay; Intelligent networks; Joining processes; Timing; Upper bound; Wires;
Conference_Titel :
Parallel Processing Symposium, 1997. Proceedings., 11th International
Conference_Location :
Genva
Print_ISBN :
0-8186-7793-7
DOI :
10.1109/IPPS.1997.580978